Non-volatile memory device and method for operating the same

ABSTRACT

A non-volatile memory device includes a plurality of input pads, a buffer configured to buffer data inputted through the plurality of the input pads in synchronization with a write enable signal, an even latch configured to store a first buffered data outputted from the buffer in response to an even write enable signal, an odd latch configured to store a second buffered data outputted from the buffer in response to an odd write enable signal, and a transfer unit configured to transfer stored data in the even latch and the odd latch to a selected bank of a plane in response to a bank selection signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2010-0050293, filed on May 28, 2010, which is incorporated herein byreference in its entirety.

BACKGROUND OF THE INVENTION

Exemplary embodiments of the present invention relate to an input/outputunit of a non-volatile memory device and a method for operating thesame.

Memory devices are divided into a volatile memory device and anon-volatile memory device according to whether data are sustained whena power source is cut off. The volatile memory device loses data when apower source is cut off, and Dynamic Random Access Memory (DRAM) andSynchronous DRAM (SDRAM) belong to the category of volatile memorydevice. The non-volatile memory device sustains data although a powersource is cut off, and flash memory device belongs to the category ofnon-volatile memory device.

FIG. 1 illustrates data inputted into input/output pads in aconventional non-volatile memory device.

Referring to FIG. 1, a write enable signal WE# toggles in a durationwhen data are inputted to input/output pads IO×8, and data are inputtedin synchronization with a rising edge of the toggling write enablesignal WE#.

In a conventional non-volatile memory device, one period tWC of thewrite enable signal WE# may be approximately 25 nm (which isapproximately 40 MHz in frequency), and the non-volatile memory devicegenerally includes 8 input/output pads IO×8. Therefore, the data may beinputted to the non-volatile memory device at a rate of approximately 40MB/s.

Meanwhile, when the data are outputted from the non-volatile memorydevice through the input/output pads IO×8, the data are outputted insynchronization with a read enable signal RE#. The output of the datathrough the input/output pads IO×8 is performed basically the same asthe input of the data therethrough except that the signal with which thedata are synchronized is not the write enable signal WE# but the readenable signal RE#.

FIG. 2 illustrates a data input/write path in a conventionalnon-volatile memory device.

Referring to FIG. 2, a write path of the conventional non-volatilememory device includes a buffer 210, a latch 220, and first to thirddemultiplexers (DEMUX) 230, 240 and 250.

The data inputted into 8 input/output pads 200 are buffered by thebuffer 210 operating in synchronization with the write enable signalWE#. Since the number of the input/output pads 200 is 8, the number ofthe output lines of the buffer 210 is 8, too.

The latch 220 latches the data obtained from the buffering in the buffer210 in synchronization with the write enable signal WE#. The latch 220has 8 output lines IDIN<0:7> as well.

The first demultiplexer 230 outputs the output of the latch 220 to thesecond demultiplexer 240 or the third demultiplexer 250 in response to abank selection signal BANK_SEL. There are 16 lines GDL_B0<0:15> andGDL_B1<0:15> between the demultiplexer 230 and the demultiplexer 240 andbetween the demultiplexer 230 and the demultiplexer 250, respectively,and a low/high selection signal L/H_SEL determines to which line theoutput of the latch 220 is to be transferred among the 16 lines. Thefollowing Table shows where an output signal of the latch 220 istransferred based on the level of the low/high selection signal L/H_SELand the bank selection signal BANK_SEL.

TABLE 1 BANK_SEL L/H_SEL Line to receive H H GDL_B1<8:15> H LGDL_B1<0:7> L H GDL_B0<8:15> L L GDL_B0<0:7>

The second demultiplexer 240 transfers the output of the firstdemultiplexer 230 on lines GDL_B0<0:15> to a bank 0 of a plane 0 and abank 0 of a plane 1. Then, the data is stored in a bank 0 of an enabledplane between the plane 0 and the plane 1.

The third demultiplexer 250 transfers the output of the firstdemultiplexer 230 on lines GDL_B1<0:15> to a bank 1 of a plane 0 and abank 1 of a plane 1. Then, the data is stored in a bank 1 of an enabledplane between the plane 0 and the plane 1.

FIG. 3 illustrates a data output/read path in the conventionalnon-volatile memory device.

Referring to FIG. 3, a read path of the conventional non-volatile memorydevice includes first and second multiplexers 310 and 320 and an outputunit 330.

The first multiplexer 310 transfers data which are outputted form a coreregion and loaded on lines GDL_B0_P0<0:15>, GDL_B1_P0<0:15>,GDL_B1_P1<0:15>, and GDL_B0_P1<0:15> outputted to 32 lines GDL_B0<0:15>and GDL_B1<0:15> in response to a plane selection signal PLANE_SEL. Whena plane 0 is selected based on the plane selection signal PLANE_SEL, thedata on lines GDL_B0_P0<0:15> is transferred to the line GDL_B0<0:15>,and the data on lines GDL_B1_P0<0:15> is transferred to the lineGDL_B1<0:15>. Also, when a plane 1 is selected based on the planeselection signal PLANE_SEL, the data on lines GDL_B0_P1<0:15> istransferred to the line GDL_B0<0:15>, and the data on linesGDL_B1_P1<0:15> is transferred to the line GDL_B1<0:15>.

The second multiplexer 320 selects a group of signals between the outputsignals of the first multiplexer 310 in response to a bank selectionsignal BANK_SEL and outputs the selected output signal to its outputterminal IDOUT<0:7>. The output lines GDL_B0<0:15> and GDL_B1<0:15> ofthe first multiplexer 310 includes 16 lines, respectively. Which line ofthe signal is to be transferred to the output terminal IDOUT<0:7> of thesecond multiplexer 320 is determined based on the low/high selectionsignal L/H_SEL. The following Table 2 shows which lines are to beselected based on the level of the low/high selection signal L/H_SEL andthe bank selection signal BANK_SEL.

TABLE 2 BANK_SEL L/H_SEL Line to be selected H H GDL_B1<8:15> H LGDL_B1<0:7> L H GDL_B0<8:15> L L GDL_B0<0:7>

The output unit 330 outputs the output data of the second multiplexer320 to an input/output pad 340 in synchronization with the read enablesignal RE#.

Although one bank includes 16 IOs in the non-volatile memory device, itmay include 8 input/output pads. Therefore, to input/output data to/fromone bank, the data is inputted/outputted over two cycles through theinput/output pads. This method, however, consumes relatively significanttime to input/output the data in the non-volatile memory device. If thenumber of the input/output pads is increased to 16, this concern may beaddressed, but increasing the number of the input/output pads leads toan increase in the corresponding area inside a chip.

SUMMARY OF THE INVENTION

An exemplary embodiment of the present invention is directed to anon-volatile memory device which inputs/outputs a data at a high speedwhile not increasing the number of input/output pads.

In accordance with an exemplary embodiment of the present invention, anon-volatile memory device includes: a plurality of input pads; a bufferconfigured to buffer data inputted through the plurality of the inputpads in synchronization with a write enable signal; an even latchconfigured to store a first buffered data outputted from the buffer inresponse to an even write enable signal; an odd latch configured tostore a second buffered data outputted from the buffer in response to anodd write enable signal; and a transfer unit configured to transferstored data in the even latch and the odd latch to a selected bank of aplane in response to a bank selection signal.

In accordance with another exemplary embodiment of the presentinvention, a non-volatile memory device includes: a core regionconfigured to store data; a selector configured to output data stored incore region from a selected bank of a selected plane in response to aplane selection signal and a bank selection signal; a transfer unitconfigured to transfer a half of output data of the selector in responseto an even read enable signal, and transfer the other half of the outputdata of the selector in response to an odd read enable signal; and anoutput unit configured to output data transferred from the transfer unitto a plurality of output pads.

In accordance with yet another exemplary embodiment of the presentinvention, a method for operating a non-volatile memory device includes:receiving data in synchronization with a write enable signal; storing afirst received data in response to an even write enable signal; storinga second received data in response to an odd write enable signal; andtransferring stored data to a selected bank of a plane in response to abank selection signal.

In accordance with yet another exemplary embodiment of the presentinvention, a method for operating a non-volatile memory device includes:outputting data of a selected bank of a selected plane from a coreregion in response to a plane selection signal and a bank selectionsignal; transferring a half of outputted data in response to an evenread enable signal, and transferring the other half of the outputteddata in response to an odd read enable signal; and outputtingtransferred data to a plurality of output pads.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates data inputted into input/output pads in aconventional non-volatile memory device.

FIG. 2 illustrates a data input path in the conventional non-volatilememory device.

FIG. 3 illustrates a data output path in the conventional non-volatilememory device.

FIG. 4 illustrates a data input path in a non-volatile memory device inaccordance with an embodiment of the present invention.

FIG. 5 illustrates a data output path in the non-volatile memory devicein accordance with the embodiment of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

The drawings are not necessarily to scale and in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When a first layer is referred to as being“on” a second layer or “on” a substrate, it not only refers to a casewhere the first layer is formed directly on the second layer or thesubstrate but also a case where a third layer exists between the firstlayer and the second layer or the substrate.

FIG. 4 illustrates a data input path in a non-volatile memory device inaccordance with an embodiment of the present invention.

Referring to FIG. 4, a non-volatile memory device includes a pluralityof input pads 400, a buffer 410, an even latch 420, an odd latch 430,and a transfer unit 440. The buffer 410 receives data that are inputtedto the plurality of the input pads 400 in synchronization with a writeenable signal WE#. The even latch 420 stores the data obtained from thebuffering in the buffer 410 in response to an even write enable signalWE_EVEN. The odd latch 430 stores the data obtained from the bufferingin the buffer 410 in response to an odd write enable signal WE_ODD. Thetransfer unit 440 transfers the data stored in the even latch 420 andthe odd latch 430 to a selected bank of a plane in response to a bankselection signal BANK_SEL.

The buffer 410 buffers the data inputted to 8 input pads 400 insynchronization with the write enable signal WE#. The buffer 410 mayinclude 8 input buffers, and 8 output lines thereof. In the embodimentof the present invention, the non-volatile memory device may operatestably although the frequency of the write enable signal WE# is doubledcompared with conventional technology. For example, when the writeenable signal WE# is approximately 40 MHz according to the conventionaltechnology, the non-volatile memory device fabricated according to theembodiment of the present invention may stably operate even if the writeenable signal WE# is approximately 80 MHz.

The even latch 420 stores the data obtained from the buffering in thebuffer 410 in response to the even write enable signal WE_EVEN. The evenwrite enable signal WE_EVEN is a signal that is enabled in aneven-numbered enable duration (e.g., pulse) of the write enable signalWE#. Referring to the bottom part of FIG. 4, the relationship betweenthe even write enable signal WE_EVEN and the write enable signal WE# maybe clearly understood. Since the even latch 420 operates insynchronization with the even write enable signal WE_EVEN, the evenlatch 420 stores data that are transferred in the order of even numbersamong the data loaded on an output line of the buffer 410.

The odd latch 430 stores the data obtained from the buffering in thebuffer 410 in response to the odd write enable signal WE_ODD. The oddwrite enable signal WE_ODD is a signal that is enabled in anodd-numbered enable duration of the write enable signal WE#. Referringto the bottom part of FIG. 4, the relationship between the odd writeenable signal WE_ODD, the even write enable signal WE_EVEN and the writeenable signal WE# may be clearly understood. Since the odd latch 430operates in synchronization with the odd write enable signal WE_ODD, theodd latch 430 stores data that are transferred in the order of oddnumbers among the data loaded on an output line of the buffer 410.

The transfer unit 440 transfers the data IDIN<8:15> stored in the evenlatch 420 and the data IDIN<0:7> stored in the odd latch 430 to theselected bank of the plane in response to the bank selection signalBANK_SEL. The transfer unit 440 may include first to thirddemultiplexers 441, 442, and 443.

The first demultiplexer 441 outputs the data IDIN<0:15> stored in theeven latch 420 and the odd latch 430 as a first bank data GDL_B0<0:15>or a second bank data GDL_B1<0:15> in response to the bank selectionsignal BANK_SEL. When a first bank is selected based on the bankselection signal BANK_SEL, the data IDIN<0:15> is output as the firstbank data GDL_B0<0:15>, and when a second bank is selected based on thebank selection signal BANK_SEL, the data IDIN<0:15> is output as thesecond bank data GDL_B1<0:15>. Since 16 data IDIN<0:15> are alreadylatched in the even latch 420 and the odd latch 430, the firstdemultiplexer 441 outputs the 16 data IDIN<0:15> as the first bank dataGDL_B0<0:15> or the second bank data GDL_B1<0:15> at one operation.

The second demultiplexer 442 transfers the first bank data GDL_B0<0:15>to a first bank BANK0 of a first plane PLANED and a first bank BANK0 ofa second plane PLANE1. Although the first bank data GDL_B0<0:15> aretransferred to both of the first plane PLANE0 and the second planePLANE1, the first bank data GDL_B0<0:15> are stored in the first bankBANK0 of an enabled plane since only one plane between the first planePLANE0 and the second plane PLANE1 is enabled.

The third demultiplexer 443 transfers the second bank data GDL_B1<0:15>to a second bank BANK1 of the first plane PLANE0 and a second bank BANK1of the second plane PLANE1. Although the second bank data GDL_B1<0:15>are transferred to both of the first plane PLANE0 and the second planePLANE1, the second bank data GDLB1<0:15> are stored in the second bankBANK1 of an enabled plane since only one plane between the first planePLANE0 and the second plane PLANE1 is enabled.

According to the embodiment of the present invention, the even dataIDIN<8:15> and the odd data IDIN<0:7> are separately latched based onthe even write enable signal WE_EVEN and the odd write enable signalWE_ODD, and in the inside, the even data IDIN<8:15> and the odd dataIDIN<0:7> are simultaneously transferred. Therefore, although thefrequency of the write enable signal WE# becomes greater than that ofthe conventional technology, stable operation may be secured. In short,although 8 input pads 400 are used, the data may be received as fast asreceived through 16 input pads 400.

FIG. 5 illustrates a data output path in the non-volatile memory devicein accordance with the embodiment of the present invention.

Referring to FIG. 5, the non-volatile memory device includes a coreregion 550, a selector 510, a transfer unit 520, and an output unit 530.The core region 550 stores data. The selector 510 outputs data of aselected bank in a selected plane from the core region 550 in responseto a plane selection signal PLANE_SEL and a bank selection signalBANK_SEL. The transfer unit 520 transfers a half OUT<0:7> of an outputdata OUT<0:15> of the selector 510 in response to an even read enablesignal RE_EVEN, and transfers the other half OUT<8:15> of the outputdata OUT<0:15> of the selector 510 in response to an odd read enablesignal RE_ODD. The output unit 530 outputs data IDOUT<0:7> transferredfrom the transfer unit 520 to a plurality of output pads 540.

The selector 510 outputs data of a selected bank in a selected plane inresponse to the plane selection signal PLANE_SEL and the bank selectionsignal BANK_SEL. The selector 510 may be formed to include a firstmultiplexer 511 and a second multiplexer 512.

The first multiplexer 511 selects the data of a plane selected based onthe plane selection signal PLANE_SEL, and outputs the selected data asits output signals GDL_B0<0:15> and GDL_B1<0:15>. When the first planePLANE0 is selected based on the plane selection signal PLANE_SEL, dataGDL_B0_P0<0:15> and GDL_B1_P0<0:15> is output as the output signalsGDL_B0<0:15> and GDL_B1<0:15>, respectively. When the second planePLANE1 is selected based on the plane selection signal PLANE_SEL, dataGDL_B0_P1<0:15> and GDL_B1_P1<0:15> is output as the output signalsGDL_B0<0:15> and GDL_B1<0:15>, respectively.

The second multiplexer 512 selects its output signal in response to thebank selection signal BANK_SEL. When the first bank BANK0 is selectedbased on the bank selection signal BANK_SEL, the output signalsGDL_B0<0:15> are output as the output data OUT<0:15>, and when thesecond bank BANK1 is selected based on the bank selection signalBANK_SEL, the output signals GDL_B1<0:15> are output as the output dataOUT<0:15>.

The transfer unit 520 transfers the half OUT<0:7> of the output dataOUT<0:15> of the selector 510 to output lines, i.e., as the dataIDOUT<0:7>, in response to the even read enable signal RE_EVEN, andtransfers the other half OUT<8:15> of the output data OUT<0:15> of theselector 510 to the output lines, i.e., as the data IDOUT<0:7>, inresponse to the odd read enable signal RE_ODD. The even read enablesignal RE_EVEN is a signal that is enabled in an even-numbered enableduration of the read enable signal RE#, and the odd read enable signalRE_ODD is a signal that is enabled in an odd-numbered enable duration ofthe read enable signal RE#. Referring to FIG. 5, the relationshipbetween the odd read enable signal RE_ODD, the even read enable signalRE_EVEN and the read enable signal RE# may be clearly understood.

The output unit 530 outputs the data IDOUT<0:7> transferred from thetransfer unit 520 to the 8 output pads 540 in synchronization with theread enable signal RE#. The output unit 530 may include 8 outputdrivers.

According to an embodiment of the present invention, which is describedabove, when a data is inputted, an even data and an odd data are latchedand transferred separately based on an even write enable signal and anodd write enable signal. Therefore, the data may be latched andtransferred stably. As a result, the stability of the input data may besecured even at a higher clock frequency.

Also, the technology of the present invention may secure the stabilityof data when the data are outputted at a high speed.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1. A non-volatile memory device, comprising: a plurality of input pads;a buffer configured to buffer data inputted through the plurality of theinput pads in synchronization with a write enable signal; an even latchconfigured to store a first buffered data outputted from the buffer inresponse to an even write enable signal; an odd latch configured tostore a second buffered data outputted from the buffer in response to anodd write enable signal; and a transfer unit configured to transferstored data in the even latch and the odd latch to a selected bank of aplane in response to a bank selection signal.
 2. The non-volatile memorydevice of claim 1, wherein the even write enable signal is a signalcorresponding to an even-numbered pulse of the write enable signal, andthe odd write enable signal is a signal corresponding to an odd-numberedpulse of the write enable signal.
 3. The non-volatile memory device ofclaim 1, wherein the transfer unit comprises: a first demultiplexerconfigured to output the stored data in the even latch and the odd latchas a first bank data or a second bank data in response to the bankselection signal; a second demultiplexer configured to output the firstbank data to a first bank of a first plane and a first bank of a secondplane; and a third demultiplexer configured to output the second bankdata to a second bank of the first plane and a second bank of the secondplane.
 4. The non-volatile memory device of claim 3, wherein the firstbank data is stored in the first bank of an activated plane between thefirst plane and the second plane, and the second bank data is stored inthe second bank of an activated plane between the first plane and thesecond plane.
 5. The non-volatile memory device of claim 3, wherein theeven and odd latches separately store the first and second buffered datato be transferred by the transfer unit at the same time.
 6. Thenon-volatile memory device of claim 1, further comprising: a core regionconfigured to store data transferred from the transfer unit; a selectorconfigured to output data stored in the core region in response to aplane selection signal and the bank selection signal; an output transferunit configured to transfer a half of output data of the selector inresponse to an even read enable signal and transfer the other half ofthe output data of the selector in response to an odd read enablesignal; and an output unit configured to output data transferred fromthe output transfer unit to a plurality of output pads.
 7. Anon-volatile memory device, comprising: a core region configured tostore data; a selector configured to output data stored in core regionfrom a selected bank of a selected plane in response to a planeselection signal and a bank selection signal; a transfer unit configuredto transfer a half of output data of the selector in response to an evenread enable signal, and transfer the other half of the output data ofthe selector in response to an odd read enable signal; and an outputunit configured to output data transferred from the transfer unit to aplurality of output pads.
 8. The non-volatile memory device of claim 7,wherein the output unit operates in synchronization with a read enablesignal.
 9. The non-volatile memory device of claim 8, wherein the evenread enable signal is a signal corresponding to an even-numbered pulseof the read enable signal, and the odd read enable signal is a signalcorresponding to an odd-numbered pulse of the read enable signal.
 10. Amethod for operating a non-volatile memory device, comprising: receivingdata in synchronization with a write enable signal; storing a firstreceived data in response to an even write enable signal; storing asecond received data in response to an odd write enable signal; andtransferring stored data to a selected bank of a plane in response to abank selection signal.
 11. The method of claim 10, wherein the evenwrite enable signal is a signal corresponding to an even-numbered pulseof the write enable signal, and the odd write enable signal is a signalcorresponding to an odd-numbered pulse of the write enable signal. 12.The method of claim 10, wherein the transferring of the stored datacomprises: outputting the stored data as a first bank data or a secondbank data in response to the bank selection signal; outputting the firstbank data to a first bank of a first plane and a first bank of a secondplane; and outputting the second bank data to a second bank of the firstplane and a second bank of the second plane.
 13. The method of claim 12,wherein the first bank data is stored in the first bank of an activatedplane between the first plane the second plane, and the second bank datais stored in the second bank of an activated plane among the first planeand the second plane.
 14. A method for operating a non-volatile memorydevice, comprising: outputting data of a selected bank of a selectedplane from a core region in response to a plane selection signal and abank selection signal; transferring a half of outputted data in responseto an even read enable signal, and transferring the other half of theoutputted data in response to an odd read enable signal; and outputtingtransferred data to a plurality of output pads.
 15. The non-volatilememory device of claim 14, wherein the transferred data are outputted insynchronization with a read enable signal.
 16. The method of claim 15,wherein the even read enable signal is a signal corresponding to aneven-numbered pulse of the read enable signal, and the odd read enablesignal is a signal corresponding to an odd-numbered pulse of the readenable signal.